
order_doublelink:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005d8 <_init>:
  4005d8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005dc:	910003fd 	mov	x29, sp
  4005e0:	94000042 	bl	4006e8 <call_weak_fn>
  4005e4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4005e8:	d65f03c0 	ret

Disassembly of section .plt:

00000000004005f0 <.plt>:
  4005f0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4005f4:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf35c>
  4005f8:	f947fe11 	ldr	x17, [x16, #4088]
  4005fc:	913fe210 	add	x16, x16, #0xff8
  400600:	d61f0220 	br	x17
  400604:	d503201f 	nop
  400608:	d503201f 	nop
  40060c:	d503201f 	nop

0000000000400610 <malloc@plt>:
  400610:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400614:	f9400211 	ldr	x17, [x16]
  400618:	91000210 	add	x16, x16, #0x0
  40061c:	d61f0220 	br	x17

0000000000400620 <__libc_start_main@plt>:
  400620:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400624:	f9400611 	ldr	x17, [x16, #8]
  400628:	91002210 	add	x16, x16, #0x8
  40062c:	d61f0220 	br	x17

0000000000400630 <__gmon_start__@plt>:
  400630:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400634:	f9400a11 	ldr	x17, [x16, #16]
  400638:	91004210 	add	x16, x16, #0x10
  40063c:	d61f0220 	br	x17

0000000000400640 <abort@plt>:
  400640:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400644:	f9400e11 	ldr	x17, [x16, #24]
  400648:	91006210 	add	x16, x16, #0x18
  40064c:	d61f0220 	br	x17

0000000000400650 <puts@plt>:
  400650:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400654:	f9401211 	ldr	x17, [x16, #32]
  400658:	91008210 	add	x16, x16, #0x20
  40065c:	d61f0220 	br	x17

0000000000400660 <free@plt>:
  400660:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400664:	f9401611 	ldr	x17, [x16, #40]
  400668:	9100a210 	add	x16, x16, #0x28
  40066c:	d61f0220 	br	x17

0000000000400670 <__isoc99_scanf@plt>:
  400670:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400674:	f9401a11 	ldr	x17, [x16, #48]
  400678:	9100c210 	add	x16, x16, #0x30
  40067c:	d61f0220 	br	x17

0000000000400680 <printf@plt>:
  400680:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400684:	f9401e11 	ldr	x17, [x16, #56]
  400688:	9100e210 	add	x16, x16, #0x38
  40068c:	d61f0220 	br	x17

0000000000400690 <putchar@plt>:
  400690:	b0000090 	adrp	x16, 411000 <malloc@GLIBC_2.17>
  400694:	f9402211 	ldr	x17, [x16, #64]
  400698:	91010210 	add	x16, x16, #0x40
  40069c:	d61f0220 	br	x17

Disassembly of section .text:

00000000004006a0 <_start>:
  4006a0:	d280001d 	mov	x29, #0x0                   	// #0
  4006a4:	d280001e 	mov	x30, #0x0                   	// #0
  4006a8:	aa0003e5 	mov	x5, x0
  4006ac:	f94003e1 	ldr	x1, [sp]
  4006b0:	910023e2 	add	x2, sp, #0x8
  4006b4:	910003e6 	mov	x6, sp
  4006b8:	580000c0 	ldr	x0, 4006d0 <_start+0x30>
  4006bc:	580000e3 	ldr	x3, 4006d8 <_start+0x38>
  4006c0:	58000104 	ldr	x4, 4006e0 <_start+0x40>
  4006c4:	97ffffd7 	bl	400620 <__libc_start_main@plt>
  4006c8:	97ffffde 	bl	400640 <abort@plt>
  4006cc:	00000000 	.inst	0x00000000 ; undefined
  4006d0:	00400b10 	.word	0x00400b10
  4006d4:	00000000 	.word	0x00000000
  4006d8:	00400b80 	.word	0x00400b80
  4006dc:	00000000 	.word	0x00000000
  4006e0:	00400c00 	.word	0x00400c00
  4006e4:	00000000 	.word	0x00000000

00000000004006e8 <call_weak_fn>:
  4006e8:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf35c>
  4006ec:	f947f000 	ldr	x0, [x0, #4064]
  4006f0:	b4000040 	cbz	x0, 4006f8 <call_weak_fn+0x10>
  4006f4:	17ffffcf 	b	400630 <__gmon_start__@plt>
  4006f8:	d65f03c0 	ret
  4006fc:	00000000 	.inst	0x00000000 ; undefined

0000000000400700 <deregister_tm_clones>:
  400700:	b0000080 	adrp	x0, 411000 <malloc@GLIBC_2.17>
  400704:	91016000 	add	x0, x0, #0x58
  400708:	b0000081 	adrp	x1, 411000 <malloc@GLIBC_2.17>
  40070c:	91016021 	add	x1, x1, #0x58
  400710:	eb00003f 	cmp	x1, x0
  400714:	540000a0 	b.eq	400728 <deregister_tm_clones+0x28>  // b.none
  400718:	90000001 	adrp	x1, 400000 <_init-0x5d8>
  40071c:	f9461021 	ldr	x1, [x1, #3104]
  400720:	b4000041 	cbz	x1, 400728 <deregister_tm_clones+0x28>
  400724:	d61f0020 	br	x1
  400728:	d65f03c0 	ret
  40072c:	d503201f 	nop

0000000000400730 <register_tm_clones>:
  400730:	b0000080 	adrp	x0, 411000 <malloc@GLIBC_2.17>
  400734:	91016000 	add	x0, x0, #0x58
  400738:	b0000081 	adrp	x1, 411000 <malloc@GLIBC_2.17>
  40073c:	91016021 	add	x1, x1, #0x58
  400740:	cb000021 	sub	x1, x1, x0
  400744:	9343fc21 	asr	x1, x1, #3
  400748:	8b41fc21 	add	x1, x1, x1, lsr #63
  40074c:	9341fc21 	asr	x1, x1, #1
  400750:	b40000a1 	cbz	x1, 400764 <register_tm_clones+0x34>
  400754:	90000002 	adrp	x2, 400000 <_init-0x5d8>
  400758:	f9461442 	ldr	x2, [x2, #3112]
  40075c:	b4000042 	cbz	x2, 400764 <register_tm_clones+0x34>
  400760:	d61f0040 	br	x2
  400764:	d65f03c0 	ret

0000000000400768 <__do_global_dtors_aux>:
  400768:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40076c:	910003fd 	mov	x29, sp
  400770:	f9000bf3 	str	x19, [sp, #16]
  400774:	b0000093 	adrp	x19, 411000 <malloc@GLIBC_2.17>
  400778:	39416260 	ldrb	w0, [x19, #88]
  40077c:	35000080 	cbnz	w0, 40078c <__do_global_dtors_aux+0x24>
  400780:	97ffffe0 	bl	400700 <deregister_tm_clones>
  400784:	52800020 	mov	w0, #0x1                   	// #1
  400788:	39016260 	strb	w0, [x19, #88]
  40078c:	f9400bf3 	ldr	x19, [sp, #16]
  400790:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400794:	d65f03c0 	ret

0000000000400798 <frame_dummy>:
  400798:	17ffffe6 	b	400730 <register_tm_clones>

000000000040079c <creat>:
  40079c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4007a0:	910003fd 	mov	x29, sp
  4007a4:	52800020 	mov	w0, #0x1                   	// #1
  4007a8:	b90037a0 	str	w0, [x29, #52]
  4007ac:	d2800300 	mov	x0, #0x18                  	// #24
  4007b0:	97ffff98 	bl	400610 <malloc@plt>
  4007b4:	f90017a0 	str	x0, [x29, #40]
  4007b8:	f94017a0 	ldr	x0, [x29, #40]
  4007bc:	f9001fa0 	str	x0, [x29, #56]
  4007c0:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  4007c4:	9130c000 	add	x0, x0, #0xc30
  4007c8:	97ffffa2 	bl	400650 <puts@plt>
  4007cc:	1400001d 	b	400840 <creat+0xa4>
  4007d0:	910073a1 	add	x1, x29, #0x1c
  4007d4:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  4007d8:	91310000 	add	x0, x0, #0xc40
  4007dc:	97ffffa5 	bl	400670 <__isoc99_scanf@plt>
  4007e0:	b9401fa0 	ldr	w0, [x29, #28]
  4007e4:	7100001f 	cmp	w0, #0x0
  4007e8:	540002a0 	b.eq	40083c <creat+0xa0>  // b.none
  4007ec:	d2800300 	mov	x0, #0x18                  	// #24
  4007f0:	97ffff88 	bl	400610 <malloc@plt>
  4007f4:	f90013a0 	str	x0, [x29, #32]
  4007f8:	b9401fa1 	ldr	w1, [x29, #28]
  4007fc:	f94013a0 	ldr	x0, [x29, #32]
  400800:	b9000001 	str	w1, [x0]
  400804:	f94013a0 	ldr	x0, [x29, #32]
  400808:	b9400001 	ldr	w1, [x0]
  40080c:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  400810:	91312000 	add	x0, x0, #0xc48
  400814:	97ffff9b 	bl	400680 <printf@plt>
  400818:	f9401fa0 	ldr	x0, [x29, #56]
  40081c:	f94013a1 	ldr	x1, [x29, #32]
  400820:	f9000801 	str	x1, [x0, #16]
  400824:	f94013a0 	ldr	x0, [x29, #32]
  400828:	f9401fa1 	ldr	x1, [x29, #56]
  40082c:	f9000401 	str	x1, [x0, #8]
  400830:	f94013a0 	ldr	x0, [x29, #32]
  400834:	f9001fa0 	str	x0, [x29, #56]
  400838:	14000002 	b	400840 <creat+0xa4>
  40083c:	b90037bf 	str	wzr, [x29, #52]
  400840:	b94037a0 	ldr	w0, [x29, #52]
  400844:	7100001f 	cmp	w0, #0x0
  400848:	54fffc41 	b.ne	4007d0 <creat+0x34>  // b.any
  40084c:	f94017a0 	ldr	x0, [x29, #40]
  400850:	f9400800 	ldr	x0, [x0, #16]
  400854:	f90017a0 	str	x0, [x29, #40]
  400858:	f94017a0 	ldr	x0, [x29, #40]
  40085c:	f900041f 	str	xzr, [x0, #8]
  400860:	f9401fa0 	ldr	x0, [x29, #56]
  400864:	f900081f 	str	xzr, [x0, #16]
  400868:	f94017a0 	ldr	x0, [x29, #40]
  40086c:	b9400001 	ldr	w1, [x0]
  400870:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  400874:	91314000 	add	x0, x0, #0xc50
  400878:	97ffff82 	bl	400680 <printf@plt>
  40087c:	f94017a0 	ldr	x0, [x29, #40]
  400880:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400884:	d65f03c0 	ret

0000000000400888 <display>:
  400888:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40088c:	910003fd 	mov	x29, sp
  400890:	f9000fa0 	str	x0, [x29, #24]
  400894:	f9400fa0 	ldr	x0, [x29, #24]
  400898:	f90017a0 	str	x0, [x29, #40]
  40089c:	f9400fa0 	ldr	x0, [x29, #24]
  4008a0:	f100001f 	cmp	x0, #0x0
  4008a4:	540001a0 	b.eq	4008d8 <display+0x50>  // b.none
  4008a8:	14000009 	b	4008cc <display+0x44>
  4008ac:	f94017a0 	ldr	x0, [x29, #40]
  4008b0:	b9400001 	ldr	w1, [x0]
  4008b4:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  4008b8:	91312000 	add	x0, x0, #0xc48
  4008bc:	97ffff71 	bl	400680 <printf@plt>
  4008c0:	f94017a0 	ldr	x0, [x29, #40]
  4008c4:	f9400800 	ldr	x0, [x0, #16]
  4008c8:	f90017a0 	str	x0, [x29, #40]
  4008cc:	f94017a0 	ldr	x0, [x29, #40]
  4008d0:	f100001f 	cmp	x0, #0x0
  4008d4:	54fffec1 	b.ne	4008ac <display+0x24>  // b.any
  4008d8:	52800140 	mov	w0, #0xa                   	// #10
  4008dc:	97ffff6d 	bl	400690 <putchar@plt>
  4008e0:	d503201f 	nop
  4008e4:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4008e8:	d65f03c0 	ret

00000000004008ec <delete>:
  4008ec:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4008f0:	910003fd 	mov	x29, sp
  4008f4:	f9000fa0 	str	x0, [x29, #24]
  4008f8:	b90017a1 	str	w1, [x29, #20]
  4008fc:	f9400fa0 	ldr	x0, [x29, #24]
  400900:	f90017a0 	str	x0, [x29, #40]
  400904:	14000004 	b	400914 <delete+0x28>
  400908:	f94017a0 	ldr	x0, [x29, #40]
  40090c:	f9400800 	ldr	x0, [x0, #16]
  400910:	f90017a0 	str	x0, [x29, #40]
  400914:	f94017a0 	ldr	x0, [x29, #40]
  400918:	b9400000 	ldr	w0, [x0]
  40091c:	b94017a1 	ldr	w1, [x29, #20]
  400920:	6b00003f 	cmp	w1, w0
  400924:	540000a0 	b.eq	400938 <delete+0x4c>  // b.none
  400928:	f94017a0 	ldr	x0, [x29, #40]
  40092c:	f9400800 	ldr	x0, [x0, #16]
  400930:	f100001f 	cmp	x0, #0x0
  400934:	54fffea1 	b.ne	400908 <delete+0x1c>  // b.any
  400938:	f94017a0 	ldr	x0, [x29, #40]
  40093c:	b9400000 	ldr	w0, [x0]
  400940:	b94017a1 	ldr	w1, [x29, #20]
  400944:	6b00003f 	cmp	w1, w0
  400948:	54000481 	b.ne	4009d8 <delete+0xec>  // b.any
  40094c:	f94017a1 	ldr	x1, [x29, #40]
  400950:	f9400fa0 	ldr	x0, [x29, #24]
  400954:	eb00003f 	cmp	x1, x0
  400958:	54000121 	b.ne	40097c <delete+0x90>  // b.any
  40095c:	f9400fa0 	ldr	x0, [x29, #24]
  400960:	f9400800 	ldr	x0, [x0, #16]
  400964:	f9000fa0 	str	x0, [x29, #24]
  400968:	f9400fa0 	ldr	x0, [x29, #24]
  40096c:	f900041f 	str	xzr, [x0, #8]
  400970:	f94017a0 	ldr	x0, [x29, #40]
  400974:	97ffff3b 	bl	400660 <free@plt>
  400978:	1400001c 	b	4009e8 <delete+0xfc>
  40097c:	f94017a0 	ldr	x0, [x29, #40]
  400980:	f9400800 	ldr	x0, [x0, #16]
  400984:	f100001f 	cmp	x0, #0x0
  400988:	540000e1 	b.ne	4009a4 <delete+0xb8>  // b.any
  40098c:	f94017a0 	ldr	x0, [x29, #40]
  400990:	f9400400 	ldr	x0, [x0, #8]
  400994:	f900081f 	str	xzr, [x0, #16]
  400998:	f94017a0 	ldr	x0, [x29, #40]
  40099c:	97ffff31 	bl	400660 <free@plt>
  4009a0:	14000012 	b	4009e8 <delete+0xfc>
  4009a4:	f94017a0 	ldr	x0, [x29, #40]
  4009a8:	f9400800 	ldr	x0, [x0, #16]
  4009ac:	f94017a1 	ldr	x1, [x29, #40]
  4009b0:	f9400421 	ldr	x1, [x1, #8]
  4009b4:	f9000401 	str	x1, [x0, #8]
  4009b8:	f94017a0 	ldr	x0, [x29, #40]
  4009bc:	f9400400 	ldr	x0, [x0, #8]
  4009c0:	f94017a1 	ldr	x1, [x29, #40]
  4009c4:	f9400821 	ldr	x1, [x1, #16]
  4009c8:	f9000801 	str	x1, [x0, #16]
  4009cc:	f94017a0 	ldr	x0, [x29, #40]
  4009d0:	97ffff24 	bl	400660 <free@plt>
  4009d4:	14000005 	b	4009e8 <delete+0xfc>
  4009d8:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  4009dc:	91318000 	add	x0, x0, #0xc60
  4009e0:	b94017a1 	ldr	w1, [x29, #20]
  4009e4:	97ffff27 	bl	400680 <printf@plt>
  4009e8:	f9400fa0 	ldr	x0, [x29, #24]
  4009ec:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4009f0:	d65f03c0 	ret

00000000004009f4 <insert>:
  4009f4:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4009f8:	910003fd 	mov	x29, sp
  4009fc:	f9000fa0 	str	x0, [x29, #24]
  400a00:	b90017a1 	str	w1, [x29, #20]
  400a04:	f9400fa0 	ldr	x0, [x29, #24]
  400a08:	f90017a0 	str	x0, [x29, #40]
  400a0c:	d2800300 	mov	x0, #0x18                  	// #24
  400a10:	97ffff00 	bl	400610 <malloc@plt>
  400a14:	f90013a0 	str	x0, [x29, #32]
  400a18:	f94013a0 	ldr	x0, [x29, #32]
  400a1c:	b94017a1 	ldr	w1, [x29, #20]
  400a20:	b9000001 	str	w1, [x0]
  400a24:	14000004 	b	400a34 <insert+0x40>
  400a28:	f94017a0 	ldr	x0, [x29, #40]
  400a2c:	f9400800 	ldr	x0, [x0, #16]
  400a30:	f90017a0 	str	x0, [x29, #40]
  400a34:	f94013a0 	ldr	x0, [x29, #32]
  400a38:	b9400001 	ldr	w1, [x0]
  400a3c:	f94017a0 	ldr	x0, [x29, #40]
  400a40:	b9400000 	ldr	w0, [x0]
  400a44:	6b00003f 	cmp	w1, w0
  400a48:	540000ad 	b.le	400a5c <insert+0x68>
  400a4c:	f94017a0 	ldr	x0, [x29, #40]
  400a50:	f9400800 	ldr	x0, [x0, #16]
  400a54:	f100001f 	cmp	x0, #0x0
  400a58:	54fffe81 	b.ne	400a28 <insert+0x34>  // b.any
  400a5c:	f94013a0 	ldr	x0, [x29, #32]
  400a60:	b9400001 	ldr	w1, [x0]
  400a64:	f94017a0 	ldr	x0, [x29, #40]
  400a68:	b9400000 	ldr	w0, [x0]
  400a6c:	6b00003f 	cmp	w1, w0
  400a70:	540003ac 	b.gt	400ae4 <insert+0xf0>
  400a74:	f9400fa1 	ldr	x1, [x29, #24]
  400a78:	f94017a0 	ldr	x0, [x29, #40]
  400a7c:	eb00003f 	cmp	x1, x0
  400a80:	54000141 	b.ne	400aa8 <insert+0xb4>  // b.any
  400a84:	f94013a0 	ldr	x0, [x29, #32]
  400a88:	f94017a1 	ldr	x1, [x29, #40]
  400a8c:	f9000801 	str	x1, [x0, #16]
  400a90:	f94017a0 	ldr	x0, [x29, #40]
  400a94:	f94013a1 	ldr	x1, [x29, #32]
  400a98:	f9000401 	str	x1, [x0, #8]
  400a9c:	f94013a0 	ldr	x0, [x29, #32]
  400aa0:	f9000fa0 	str	x0, [x29, #24]
  400aa4:	14000018 	b	400b04 <insert+0x110>
  400aa8:	f94017a0 	ldr	x0, [x29, #40]
  400aac:	f9400400 	ldr	x0, [x0, #8]
  400ab0:	f94013a1 	ldr	x1, [x29, #32]
  400ab4:	f9000801 	str	x1, [x0, #16]
  400ab8:	f94013a0 	ldr	x0, [x29, #32]
  400abc:	f94017a1 	ldr	x1, [x29, #40]
  400ac0:	f9000801 	str	x1, [x0, #16]
  400ac4:	f94017a0 	ldr	x0, [x29, #40]
  400ac8:	f9400401 	ldr	x1, [x0, #8]
  400acc:	f94013a0 	ldr	x0, [x29, #32]
  400ad0:	f9000401 	str	x1, [x0, #8]
  400ad4:	f94017a0 	ldr	x0, [x29, #40]
  400ad8:	f94013a1 	ldr	x1, [x29, #32]
  400adc:	f9000401 	str	x1, [x0, #8]
  400ae0:	14000009 	b	400b04 <insert+0x110>
  400ae4:	f94017a0 	ldr	x0, [x29, #40]
  400ae8:	f94013a1 	ldr	x1, [x29, #32]
  400aec:	f9000801 	str	x1, [x0, #16]
  400af0:	f94013a0 	ldr	x0, [x29, #32]
  400af4:	f94017a1 	ldr	x1, [x29, #40]
  400af8:	f9000401 	str	x1, [x0, #8]
  400afc:	f94013a0 	ldr	x0, [x29, #32]
  400b00:	f900081f 	str	xzr, [x0, #16]
  400b04:	f9400fa0 	ldr	x0, [x29, #24]
  400b08:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400b0c:	d65f03c0 	ret

0000000000400b10 <main>:
  400b10:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400b14:	910003fd 	mov	x29, sp
  400b18:	97ffff21 	bl	40079c <creat>
  400b1c:	f9000fa0 	str	x0, [x29, #24]
  400b20:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  400b24:	91320000 	add	x0, x0, #0xc80
  400b28:	97fffeca 	bl	400650 <puts@plt>
  400b2c:	910053a1 	add	x1, x29, #0x14
  400b30:	90000000 	adrp	x0, 400000 <_init-0x5d8>
  400b34:	91310000 	add	x0, x0, #0xc40
  400b38:	97fffece 	bl	400670 <__isoc99_scanf@plt>
  400b3c:	b94017a0 	ldr	w0, [x29, #20]
  400b40:	2a0003e1 	mov	w1, w0
  400b44:	f9400fa0 	ldr	x0, [x29, #24]
  400b48:	97ffffab 	bl	4009f4 <insert>
  400b4c:	f9000fa0 	str	x0, [x29, #24]
  400b50:	f9400fa0 	ldr	x0, [x29, #24]
  400b54:	97ffff4d 	bl	400888 <display>
  400b58:	52800061 	mov	w1, #0x3                   	// #3
  400b5c:	f9400fa0 	ldr	x0, [x29, #24]
  400b60:	97ffff63 	bl	4008ec <delete>
  400b64:	f9000fa0 	str	x0, [x29, #24]
  400b68:	f9400fa0 	ldr	x0, [x29, #24]
  400b6c:	97ffff47 	bl	400888 <display>
  400b70:	52800000 	mov	w0, #0x0                   	// #0
  400b74:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400b78:	d65f03c0 	ret
  400b7c:	00000000 	.inst	0x00000000 ; undefined

0000000000400b80 <__libc_csu_init>:
  400b80:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400b84:	910003fd 	mov	x29, sp
  400b88:	a901d7f4 	stp	x20, x21, [sp, #24]
  400b8c:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf35c>
  400b90:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf35c>
  400b94:	91374294 	add	x20, x20, #0xdd0
  400b98:	913722b5 	add	x21, x21, #0xdc8
  400b9c:	a902dff6 	stp	x22, x23, [sp, #40]
  400ba0:	cb150294 	sub	x20, x20, x21
  400ba4:	f9001ff8 	str	x24, [sp, #56]
  400ba8:	2a0003f6 	mov	w22, w0
  400bac:	aa0103f7 	mov	x23, x1
  400bb0:	9343fe94 	asr	x20, x20, #3
  400bb4:	aa0203f8 	mov	x24, x2
  400bb8:	97fffe88 	bl	4005d8 <_init>
  400bbc:	b4000194 	cbz	x20, 400bec <__libc_csu_init+0x6c>
  400bc0:	f9000bb3 	str	x19, [x29, #16]
  400bc4:	d2800013 	mov	x19, #0x0                   	// #0
  400bc8:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400bcc:	aa1803e2 	mov	x2, x24
  400bd0:	aa1703e1 	mov	x1, x23
  400bd4:	2a1603e0 	mov	w0, w22
  400bd8:	91000673 	add	x19, x19, #0x1
  400bdc:	d63f0060 	blr	x3
  400be0:	eb13029f 	cmp	x20, x19
  400be4:	54ffff21 	b.ne	400bc8 <__libc_csu_init+0x48>  // b.any
  400be8:	f9400bb3 	ldr	x19, [x29, #16]
  400bec:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400bf0:	a942dff6 	ldp	x22, x23, [sp, #40]
  400bf4:	f9401ff8 	ldr	x24, [sp, #56]
  400bf8:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400bfc:	d65f03c0 	ret

0000000000400c00 <__libc_csu_fini>:
  400c00:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400c04 <_fini>:
  400c04:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400c08:	910003fd 	mov	x29, sp
  400c0c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400c10:	d65f03c0 	ret
